1. Field of the Invention
This invention relates to computer systems, and more particularly, to accessing memory in computer systems.
2. Description of the Related Art
As integrated circuit (IC) technology has advanced, a greater number of functions may be integrated onto a single chip. In the field of processors, higher levels of integration have led to the design and fabrication of system-on-a-chip (SOC) type devices. In various implementations, an SOC may include one or more processor cores, a graphics processing unit, various input/output (I/O) ports, and a memory controller. When such an SOC is implemented in a computer system, communication with a system random access memory (RAM) by other components (e.g., processor cores) may be coordinated through the memory controller.
The various components on an SOC, including the memory controller, may operate according to a clock signal that is different than that used to synchronize transfers of data to and from system RAM (e.g., in different clock domains). Furthermore, the frequency of the respective clock signals may be varied during system operation. For example, the frequency of a memory controller clock signal may be reduced to conserve power. Thus, it is possible that the respective clock signals used on the SOC (including that used by the memory controller) and the system RAM may be mismatched in frequency. This may affect the possible rates of data transfer between the SOC (and components thereof) and the system RAM, and in turn, may thus affect the performance of the computer system in which the SOC and system RAM are implemented.
Because clock signals in different domains may be mismatched in frequency, various hardware schemes may be implemented to perform bandwidth matching of information crossing from one clock domain to another. This may reduce the performance penalty that might otherwise be incurred when respective clock signals in different domains are mismatched in frequency.